GPR5

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Interpret as GPR5

WDOG2_MASK=WDOG2_MASK_0, VREF_1M_CLK_GPT1=VREF_1M_CLK_GPT1_0, ENET2_EVENT3IN_SEL=ENET2_EVENT3IN_SEL_0, VREF_1M_CLK_GPT2=VREF_1M_CLK_GPT2_0, ENET_EVENT3IN_SEL=ENET_EVENT3IN_SEL_0, WDOG1_MASK=WDOG1_MASK_0, GPT2_CAPIN1_SEL=GPT2_CAPIN1_SEL_0, GPT2_CAPIN2_SEL=GPT2_CAPIN2_SEL_0

Description

GPR5 General Purpose Register

Fields

WDOG1_MASK	WDOG1 Timeout Mask 0 (WDOG1_MASK_0): WDOG1 Timeout behaves normally 1 (WDOG1_MASK_1): WDOG1 Timeout is masked
WDOG2_MASK	WDOG2 Timeout Mask 0 (WDOG2_MASK_0): WDOG2 Timeout behaves normally 1 (WDOG2_MASK_1): WDOG2 Timeout is masked
GPT2_CAPIN1_SEL	GPT2 input capture channel 1 source select 0 (GPT2_CAPIN1_SEL_0): source from GPT2_CAPTURE1 1 (GPT2_CAPIN1_SEL_1): source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)
GPT2_CAPIN2_SEL	GPT2 input capture channel 2 source select 0 (GPT2_CAPIN2_SEL_0): source from GPT2_CAPTURE2 1 (GPT2_CAPIN2_SEL_1): source from ENET2_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)
ENET_EVENT3IN_SEL	ENET input timer event3 source select 0 (ENET_EVENT3IN_SEL_0): event3 source input from ENET_1588_EVENT3_IN 1 (ENET_EVENT3IN_SEL_1): event3 source input from GPT2.GPT_COMPARE1
ENET2_EVENT3IN_SEL	ENET2 input timer event3 source select 0 (ENET2_EVENT3IN_SEL_0): event3 source input from ENET2_1588_EVENT3_IN 1 (ENET2_EVENT3IN_SEL_1): event3 source input from GPT2.GPT_COMPARE2
VREF_1M_CLK_GPT1	GPT1 1 MHz clock source select 0 (VREF_1M_CLK_GPT1_0): GPT1 ipg_clk_highfreq driven by IPG_PERCLK 1 (VREF_1M_CLK_GPT1_1): GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock
VREF_1M_CLK_GPT2	GPT2 1 MHz clock source select 0 (VREF_1M_CLK_GPT2_0): GPT2 ipg_clk_highfreq driven by IPG_PERCLK 1 (VREF_1M_CLK_GPT2_1): GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock

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